Functional validation (verification) of complex IC designs is an activity that currently consumes a majority of the engineering man-hours for creating a semiconductor design. Verification entails checking the output of a design implementation with that expected by a design reference model. The checking can be either at an abstract level using a high-level reference model, or it can involve checking signals on a cycle-by-cycle basis against a cycle-accurate reference model. The validation process depends upon having two independently-created implementations of the same specification to reduce the probability that a violation of the specification is accepted due to a common-mode failure in both the implementations.
This invention pertains to checking a plurality of design modules against a plurality of modules within a cycle-accurate reference model. The use of cycle-accurate reference models is unusual within the industry because:                1. There is a considerable overhead involved in maintaining a cycle-accurate reference model beyond that for maintaining an abstract reference model. This overhead increases proportionately to the degree of flux of the architectural specification of the design.        2. Implementing a new architecture requires a parallel effort to create a cycle-accurate reference model; this parallel effort has approximately the same degree of difficulty as the implementation being tested for the architecture.        3. In cases where a re-implementation occurs of an existing architecture, the original implementation cannot usually be used as a reference model since there are usually changes to the feature set, such as adding new features or fixing defects, that render the original implementation inaccurate as a reference model.        
Thus, the current invention is useful only when a cycle-accurate implementation of a stable architecture can be used as a reference model for a re-implementation of that architecture.
Since validation occupies such a time-consuming portion of the development of complex ICs, it is important to begin the validation process as soon as possible in the design cycle. The present invention greatly facilitates the early testing of design modules by automating the repetitive task of generating test benches. Furthermore, our method uses description files to specify how the testing of a design module is to proceed; these description files act as a precise definition of the interfaces between design modules.
This application claims the benefits of the earlier filed U.S. Provisional Application Ser. No. 60/893,028, filed 5 Mar. 2007, which is incorporated by reference for all purposes into this specification.